The IC ECAD Design Studio at EE-UCR

The UCR IC ECAD Design Studio has the following industrial prevailing IC ECAD simulation tools from the leading EDA vendors, such as CADENCE Design Systems and Synopsys, Inc., etc.


The Custom IC Bundle:

Design Entry

  • Cadence SKILL development environment
  • Virtuoso schematic composer VHDL interface
  • Virtuoso schematic composer Verilog interface
  • Affirma analog circuit optimizer option
  • Virtuoso schematic composer
  • Affirma analog design environment


  • Virtuoso Compactor
  • Virtuoso -XL layout editor
  • Virtuoso chip assembly router

Physical Verification

  • Dracula interactive debugging enviroment
  • Assura RC network reducer option
  • Dracula physical verification and parasitic extraction suite
  • Assura Diva physical verification and parasitic extraction suite71520

Circuit Simulation

  • Virtuoso HSPICE interface
  • Virtuoso schematic composer netlister to Affirma analog circuit simulator
  • Affirma analog statistical analysis option
  • Affirma analog corner analysis option
  • Affirma mixed-signal simulation interface option
  • Affirma analog circuit simulator
  • Affirma RF simulation option
  • Affirma RF circuit package modeler
  • Affirma HSPICE interface


  • Virtuoso schematic to design compiler integration
  • Virtuoso EDIF 200 reader
  • Virtuoso EDIF 300 connectivity reader and writer
  • Virtuoso EDIF 300 schematic reader and writer
  • Virtuoso Stream interface
  • Virtuoso CIF reader
  • Virtuoso CIF writer
  • Cadence Design Framework integrator's toolkit
  • GDT interface
  • GDSII/EDIF interface
  • LEF/DEF interface
  • Mentor SDL interface
  • SPICE interface


  • Affirma Mixed-Signal Back-Annotation Interface
  • Affirma Substrate Coupling Analisys

The Deep Submicron Design Bundle:

Place & Route

  • Virtuoso custom placer
  • Virtuoso chip assembly router
  • Envisia clock tree generator
  • Envisia gate array place and route
  • Envisia place and route system with signal and design integrity


  • Affirma timing analyzer for full custom design
  • Assura interconnect parasitic extractor standalone package


  • Envisia physical design planner DSM(Pillar)
  • Envisia logic design planner DSM

Design and Verification Bundle:

Functional Simulation

  • Affirma native compiled Verilog simulator
  • Affirma native compiled VHDL simulator


  • Envisia synthesis tool

System Level Design

  • Cierto hardware design system 2000
  • Cierto multimedia design kit Cierto signal processing worksystem 2000

Wireless System-Level Verification

  • GSM verification environment
  • IS 136 verification environment
  • Cierto signal processing worksystem link to NC simulators
  • PCS/CDMA verification environment

PCB Systems Bundle:


  • Concept HDL expert
  • PCB librarian expert
  • Affirma native compiled Verilog simulator

PCB Layout and Analysis

  • PCB Design expert

Analog/Mixed-Signal PCB

  • PCB mixed-signal expert

High Speed Design

  • SPECTRAQuest SI expert
  • Digital logic SI library
  • Memry SI library
  • FPGA SI library
  • Microprocessor SI library


  • Cierto communication library - floating point
  • Cierto communication library -fixed point
  • Cierto wideband library
  • Cierto SPW model manager

Agilent/HP Tools





Synopsys Tools















Other EDA Tools