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In Publications


In Briefs

  1. IC circuit noise performance may be degraded significantly by ESD protection as indicated by our recent research data. Low-noise ESD structures are essential to advanced RF IC chips.

References: "ESD-induced circuit performance degradation in RFICs", submitted to IEEE ESREF, Oct. 2001.


  1. IC chip performance, both clock speed and other general specifications, may deteriorate dramatically if traditional NMOS ESD protections are used. Such performance degradation can be recovered substantially by using low-parasitic compact ESD protection structures.


1. SRC Report, P000375, 17 March 2000.

2. "A comparison study of ESD protection for RFICs: performance vs. parasitics", Proc. IEEE RFIC Symp., pp. 253-258, 2000.


  1. Caution, VDSM IC designers! The "classic" ESD design rule of "minimum" source-contact-to-gate-spacing (SCGS) will no longer hold in deep-sub-micron design due to micro-heat spreading and phonon heat transport effects. One has to conduct detailed simulation to ensure chip performance.

References: SRC Report, P000375, 17, March 2000.


4.      Questions: In VDSM IC designs, how can I optimize metal interconnects for ESD protection? Does it sound reasonable for a designer to follow the traditional "rule-of-thumb" that suggests 20um or "as wide as possible" a metal line in ESD blocks, from 0.5um to 0.35um to 0.25um to 0.18um to 0.13, and all the way to sub-0.1um?!

Answer: Of course NOT! Similar to the global interconnect RC delay problem faced in VLSI designs, recent research data show intolerable ESD interconnect RC delay effects in advanced high-speed designs. In addition, by using mixed-mode simulation approaches, it seems to be possible to optimize ESD interconnect design to achieve both adequate ESD protection and minimum ESD RC delay effect. Of course, it is NOT an easy task, either!


1. "On impacts of ESD protection structure on circuit performance in Al and Cu interconnects", Proc. IEEE EIT, paper 106-3, 2000.

2. "A new integrated metal-semiconductor simulation methodology for on-chip electrostatic discharge protection optimization", Proc. IEEE/IFIP WCC-ICDA, pp. 81-85, 2000.


  1. IC designers, looking for low-parasitic compact ESD protection for mixed-signal and RF IC chips? -- The following designs offer robustness protection, low ESD-induced parasitic effects, small sizes, and were proven working. Hope it helps.


1. "On a dual-direction on-chip electrostatic discharge protection structure", in press, IEEE Trans. Electron Dev., Vol 48, No. 4, April 2000.

2. "A novel on-chip electrostatic discharge protection design for RFICs", J. Microelectronics, Vol 32/3, Elsevier Science, pp. 189-195, 2000.


  1. I would like to have an ESD solution with good performance, low parasitic, and adjustable low trigger voltage for my chip. -- The following ones might be interesting to you.


1. "An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology", IEEE J. Solid-State Circuits, Vol 35, No. 1, pp. 40-45, January 2000.

2. "A ESD protection circuit for mixed-signal ICs", in press, Proc. IEEE CICC, May, 2000.


  1. Sure, as a VDSM IC designer, you need an optimized ESD protection that delivers less parasitic stuff and takes less Si asset, even more, is layout friendly. -- Check with the following bond pad oriented designs.


1."A pad-oriented novel electrostatic discharge protection structure for mixed-signal ICs", submitted to IEEE CSCC'00, July 2000.

2."Another one", in preparation, somewhere, 2000.


  1. Is there any comprehensive tutorial/review paper on advanced on-chip ESD protection design, specially tuned for IC designers and showing practical simulation/design/layout skills? -- Hoep this one might help.

References: "A tutorial for on-chip ESD protection design for ICs", in preparation, coming soon, 2000.