RESEARCH DATA SHARING
At LICS, we fully believe the whole purpose of any research is to benefit the human society as a whole. The kind of For-Research research is never our goal; neither is the For-Profit research being our motivation. Consequently, the LICS-ers are more than happy to share with our academic and industrial colleagues our newest research outcomes. There could be many different ways in achieving research data dissemination, such as, paper publications, web-posting of interesting results, on-site technical seminars, training lectures, consulting, and direction conversations via email or voice, etc. For those research projects sponsored by our industrial partners, we are fully aware of the IP concerns and completely bound to the NDA agreements upon which we agree. The bottom line, we believe that the essence of the Information Technology is about communication and information exchange.
RECENT RESEARCH RESULTS FROM LICS:
References: "ESD-induced circuit performance degradation in RFICs", submitted to IEEE ESREF, Oct. 2001.
1. SRC Report, P000375, 17 March 2000.
2. "A comparison study of ESD protection for RFICs: performance vs. parasitics", Proc. IEEE RFIC Symp., pp. 253-258, 2000.
References: SRC Report, P000375, 17, March 2000.
4. Questions: In VDSM IC designs, how can I optimize metal interconnects for ESD protection? Does it sound reasonable for a designer to follow the traditional "rule-of-thumb" that suggests 20um or "as wide as possible" a metal line in ESD blocks, from 0.5um to 0.35um to 0.25um to 0.18um to 0.13, and all the way to sub-0.1um?!
Answer: Of course NOT! Similar to the global interconnect RC delay problem faced in VLSI designs, recent research data show intolerable ESD interconnect RC delay effects in advanced high-speed designs. In addition, by using mixed-mode simulation approaches, it seems to be possible to optimize ESD interconnect design to achieve both adequate ESD protection and minimum ESD RC delay effect. Of course, it is NOT an easy task, either!
1. "On impacts of ESD protection structure on circuit performance in Al and Cu interconnects", Proc. IEEE EIT, paper 106-3, 2000.
2. "A new integrated metal-semiconductor simulation methodology for on-chip electrostatic discharge protection optimization", Proc. IEEE/IFIP WCC-ICDA, pp. 81-85, 2000.
1. "On a dual-direction on-chip electrostatic discharge protection structure", in press, IEEE Trans. Electron Dev., Vol 48, No. 4, April 2000.
2. "A novel on-chip electrostatic discharge protection design for RFICs", J. Microelectronics, Vol 32/3, Elsevier Science, pp. 189-195, 2000.
1. "An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology", IEEE J. Solid-State Circuits, Vol 35, No. 1, pp. 40-45, January 2000.
2. "A ESD protection circuit for mixed-signal ICs", in press, Proc. IEEE CICC, May, 2000.
1."A pad-oriented novel electrostatic discharge protection structure for mixed-signal ICs", submitted to IEEE CSCC'00, July 2000.
2."Another one", in preparation, somewhere, 2000.
References: "A tutorial for on-chip ESD protection design for ICs", in preparation, coming soon, 2000.