An Investigation into Complex ESD-Circuit Interactions at Chip Level

This is an on-going project to investigate the complex, but largely over-looked, ESD-circuit interaction problem. In high-speed VDSM designs, one ought to consider the ESD-induced parasitic effects on the core circuit performance, in addition to the commonly considered circuit-to-ESD influences. The new chip-level ESD design verification CAD tools, currently under development at IEL, will be vital to addressing such issues. New sponsors are welcome to work with us collaboratively.

REFERENCES:

• H. G. Feng, K. Gong and A. Wang, " ESD Protection Design Using Copper Interconnects: More Robustness and Less Parasitics", Proc. IEEE RFIC Symp., pp235-238, 2000.

• K. Gong, H. Feng and A. Wang, " ESD-induced Circuit Performance Degradation in RFICs ", in preparation, 2001.