A low-Vt compact ESD protection circuit for mixed-signal and RF ICs

This project, currently still on-going, develops novel compact ESD protection circuit solutions, featuring low-triggering voltage, small size, high ESD-to-Si ratio, high ESDV protection, and much reduced ESD-induced parasitic effects. It triggering voltage can be well controlled by a trigger-assisting sub-circuit. This new design concept is a good option for advanced mixed-signal and RF IC applications. The novel design is guided by our new mixed-mode ESD simulation-design methodology.

REFERENCES:

• A. Z. Wang and C. Tsay, " An on-Chip ESD Protection Circuit with Low Trigger-Voltage in BiCMOS Technology", IEEE J. Solid-State Circuits, Vol. 36, Number 1, pp.40-45, January 2001.