• 3D Heterogeneous Integration Technologies for ICs
  • Integrated Design-for-Reliability (iDfR) for ICs and Systems
  • Analog/RF/Mixed-Signal ICs and SoCs
  • IC CAD & Modeling
  • Emerging Nano Devices and Circuits
  • LED-Based Visible Light Communication (VLC) and Positioning (VLP)
  • Biomedical Electronics





  1. Adaptive Hi-h Enhancement PA Technique
  2. Graphene-based ESD protection
  3. Nano Crystal Quantum Dot (NC-QD) ESD Protection
  4. Nano Crossbar ESD Protection, a PhD thesis project,
  5. Stacked-Via Magnetic-Cored RF Inductors, a PhD thesis project,
  6. Precision V-reference circuit design,
  7. 1-UWB system simulation,
  8. 1-UWB SoC with integrated ADC, a PhD thesis project,
  9. Single-Chip RF Transceiver Front-end Design, a PhD thesis project.
  10. ESD-aware RFIC design methodology, a PhD thesis project.
  11. 24Gz RFID SoC, a PhD thesis project.
  12. UWB SoC design, a PhD thesis project.
  13. Gsps ADC for UWB communications, a PhD thesis project
  14. Resolution/speed/power-optimized ADC, a PhD thesis project
  15. 10b 500Msps ADC, sponsored by Skyworks.
  16. 14b 100Msps ADC, sponsored by Skyworks.
  17. ESDExtractor: New CAD algorithm for full-chip ESD design extraction, sponsored by NSF.
  18. ESDInspector: A New Layout Level Full-Chip ESD protection Circuit Design Verification Tool, sponsored by NSF.
  19. ESDZapper: CAD Tool for Full-Chip ESD Protection Circuit Testing Simulation, sponsored by NSF.
  20. ESDSimulator: A New Schematic Level Full-Chip ESD Protection Circuit Design Verification Algorithm and Tool, sponsored by NSF.
  21. Parallel Section-wise ESD Device Modeling, sponsored by NSF.
  22. Novel 0-leakage ESD Protection Structure for Nano Designs.
  23. A new 3D Mixed-Mode ESD Simulation-Design Methodology, sponsored by NSF.
  24. ESDcat: A CAD Package for Whole-Chip ESD Protection Design Synthesis and Verification, sponsored by NSF.
  25. 15+KV on-Chip ESD Protection Design for RS232 Chips, sponsored by National Semi.
  26. A Novel all-in-one Compact Electrostatic Discharge Protection Structure for Mixed-Signal and RF ICs, sponsored by IIT-ESRIF.
  27. SCR Copper Design Contest 1999-2000, sponsored by SRC, UMC & Novallus.
  28. High-Speed ADC Circuits for wireless communications, sponsored by AKM.
  29. Novel on-Chip Inductors with Cores for Single-Chip RF
  30. A High-Performance LNA with on-Chip Transformer for RF
  31. A 2D Mixed-Mode ESD Simulation-Design Methodology
  32. Advanced RF ESD Protection Design
  33. Single-Chip CMOS RF SoC, sponsored by RF Integrated Corp.
  34. An Investigation into complex ESD-Circuit Interactions at Chip Level, sponsored by NSF.
  35. ESD Protection for Nano Technology, sponsored by NSF.
  36. Low-parasitic protection circuits for a 0.35 CMOS technology, sponsored by AKM.
  37. A low-Vt compact ESD protection circuit for mixed-signal and RF ICs.
  38. Bond-pad oriented novel compact protection for VDSM mixed-signal and RF ICs
  39. Advanced ESD protection circuits for RF ICs, sponsored by AKM.
  40. Vt1 ~ t1 characteristics in ESD protection design, sponsored by the ESD Association.